CVE-2025-45006

9.1 CRITICAL

Published: July 01, 2025 Modified: April 15, 2026

Description

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

AI Explanation

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CVSS v3.x Details

0.0 Low Medium High Critical 10.0

Vector String

CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H

References to Advisories, Solutions, and Tools

Patch Vendor Advisory Exploit Third Party Advisory

https://github.com/chipsalliance/rocket-chip.git

Source: cve@mitre.org

https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md

Source: cve@mitre.org

https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications

Source: cve@mitre.org

3 reference(s) from NVD

Quick Stats

CVSS v3 Score

9.1 / 10.0

EPSS (Exploit Probability)

0.1%

19th percentile

Exploitation Status

Not in CISA KEV

Weaknesses (CWE)

CWE-266

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